Reducing Power Consumption of the Issue Logic

A technique to reduce the power consumption of the issue logic of superscalar processors is presented. We have evaluated the power consumption of diierent parts of the architecture through a detailed cycle-by-cycle simulation. The results show that one of the principal power consumption's factor in a superscalar processor is the hardware devoted to extract parallelism from applications. We propose a technique to dynamically resize the instruction queue based on the existing parallelism in diierent periods of the execution. With the proposed method we can save about 15 per cent on the total power consumption in the processor. 1 Introduction The constant increase in integration of ICs and the higher frequencies of operation of modern microarchitectures result in a signiicant increment of power consumption even though technology and voltage scaling approaches are adopted to mitigate this eeect. Modern architectures like Alpha 21364 and PowerPC 704 are now on the range of 85 to 100 Watt 1]. Issues such as the high fraction of package cost on total chip, portability, reliability and the today's high demand of mobile devices ask for new evaluation methods and techniques to attack this problem. The current prevision show that the energy battery will not increase drastically in the near future due to actual technology problems and for safety reasons 2]. On the other hand, portable devices of the next generations will include several multimedia functionalities and will be able to sustain high performance through powerful system architecture 3]. The historical trend in the design of computer architectures was based on performance with minor considerations regarding power. Today's new generation CAD tools for VLSI design likePoweMill 4] and QuickPower 5] allow to evaluate the power consumption at diierent points of the design, from the high level deenition through the circuit level. This allow to maintain a continuous feedback between the power requirements and the